One of the primary steps in the fabrication of modern semiconductor devices is the formation of a thin film on a semiconductor substrate by chemical reaction of gases. Such a deposition process is referred to generally as chemical vapor deposition (“CVD”). Conventional thermal CVD processes supply reactive gases to the substrate surface, where heat-induced chemical reactions take place to produce a desired film. Plasma-enhanced CVD (“PECVD”) techniques, on the other hand, promote excitation and/or dissociation of the reactant gases by the application of radio-frequency (“RF”) energy to a reaction zone near the substrate surface, thereby creating a plasma.
Any of these CVD techniques may be used to deposit conductive or insulative films during the fabrication of integrated circuits. For applications such as the deposition of insulating films as premetal or intermetal dielectric layers in an integrated circuit or for shallow trench isolation, one important physical property of the CVD film is its ability to fill gaps completely between adjacent structures without leaving voids; this property is referred to as the film's gapfill capability. Gaps that may require filling include spaces between adjacent raised structures such as transistor gates, conductive lines, etched trenches, or the like.
As semiconductor device geometries have decreased in size over the years, the ratio of the height of such gaps to their width, the so-called “aspect ratio,” has increased dramatically. Gaps having a combination of high aspect ratio and a small width present a particular challenge for semiconductor manufacturers to fill completely. In short, the challenge usually is to prevent the deposited film from growing in a manner that closes off the gap before it is filled. Failure to fill the gap completely results in the formation of voids in the deposited layer, which may adversely affect device operation such as by trapping undesirable impurities. The semiconductor industry has accordingly been searching aggressively for techniques that may improve gapfill capabilities, particularly with high-aspect-ratio small-width gaps.
One of the more aggressive gapfill applications in modern integrated circuits is isolating adjacent active devices using a process referred to as shallow trench isolation (STI). STI isolation techniques generally etch shallow trenches in the silicon substrate, fill the etched trenches with a dielectric material and then planarize the structure back to the silicon surface in the areas outside the trench. Active devices can then be built in the spaces or islands between the isolation regions.
FIGS. 1A–1F are simplified cross-sectional views of a partially completed integrated circuit illustrating a common STI formation process formed on a silicon substrate 10. Referring to FIG. 1A, a typical shallow trench isolation structure is created by first forming a thin pad oxide layer 12 over the surface of substrate 10 and then forming a silicon nitride layer 14 over pad oxide layer 12. The nitride layer acts as a hard mask during subsequent photolithography processes and the pad oxide layer provides adhesion of the nitride to the silicon substrate and protects the substrate when the nitride layer is removed near the end of the STI formation process.
A series of etch steps are then performed using standard photolithography techniques to pattern the nitride and oxide layers and form trenches or gaps 22 in silicon substrate 10. The photoresist (not shown) is then removed and the structure is subjected to an ion implantation and/or H2 treatment step as shown in FIG. 1B.
Next, a trench lining layer 16, such as an in situ steam generation (ISSG) oxide or other thermal oxide layer is usually formed as shown in FIG. 1C. The formation of lining layer 16 removes etch damage and/or residue from the interior of the trench and passivates the silicon surface of the trench provising a stable interface between the silicon and the trench fill material. The formation of lining layer 16 also rounds the corners of the pad, which may improve device performance as a sharp corner tends to enhance the electric field lines at the corner and degraded MOSFET turn-off characteristics.
Some STI applications form one or more additional lining layers after the formation of oxide layer 16. For example, in FIG. 1D a silicon nitride layer 18 and medium temperature oxide layer 20 are shown. Such lining layers help minimize dopant distribution and minimize the formation of a dent or divot between the silicon substrate and the filled trench as discussed later with respect to FIG. 1F. The material of the additional lining layers may also be selected to improve device performance and minimize silicon bending and other issues.
Referring to FIG. 1E, trenches 22 are then filled with an insulating material, such as gapfill silicon oxide layer 24, using a deposition process that has good gapfill properties. Ideally, the gapfill process completely fills trench 22 so that no air gaps or voids are formed in the trench. Also, it is desirable to minimize physical damage to the trench walls and minimize stress at the silicon/STI structure interface that may occur during the trench fill process.
One or more additional steps including chemical mechanical polishing (CMP) are then used to remove nitride layer 14 and pad oxide layer 12 and level the gapfill oxide 24 to the top of the trench (surface 26) as shown in FIG. 1F. The remaining insulating oxide in the trenches provides electrical isolation between active devices formed on neighboring islands of silicon. During the planarization process, the differing physical properties of the different materials that form the STI structure generally result in the formation of small dents or divots 28 on the surface of the structure at the interface between the silicon substrate and the gapfill dielectric. Minimizing the size of such dents or divots is an important device performance criteria for some integrated circuits.
A variety of different gapfill techniques have been developed to address such situations. Despite the many successes achieved in this area, semiconductor manufacturers are continuously researching alternative techniques to fill such gaps as well as improved techniques to fill the even more aggressive aspect ratio gaps that will likely be required in future processes.